The disclosure generally relates to a flash memory device, and, more particularly, to a method for operating a charge trap flash memory device.
In order to prevent mutual interference between adjacent memory cells, a charge trap flash memory having a new cell structure has been developed which performs a program operation and an erase operation by using a charge trapping layer, instead of a floating gate. A charge trap flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) or metal-alumina-nitride-oxide-silicon (MANOS) structure, which is widely used as a charge trapping element, includes a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode, which are sequentially formed over a substrate with a channel region.
FIG. 1 illustrates a cross-sectional view of a typical flash memory device having a charge trapping layer.
Referring to FIG. 1, a tunneling layer 110 is formed over a substrate 100, such as a silicon (Si) substrate. The tunneling layer 110 is formed as an oxide film. Impurity regions 102, such as source/drain regions, are disposed in the substrate 100 and spaced apart from each other by a predetermined distance. A channel region 104 is disposed between the impurity regions 102. A silicon nitride film used as a charge trapping layer 120 is formed over the tunneling layer 110. An insulation film used as a blocking layer 130, and a control gate electrode 140 are sequentially disposed over the charge trapping layer 120.
A program operation is performed by positively charging the control gate electrode 140 and applying an appropriate bias to the impurity regions 102. Hot electrons from the substrate 100 are trapped in trap sites inside the charge trapping layer 120. In this way, a memory cell is programmed. On the other hand, an erase operation is performed by negatively charging the control gate electrode 140 and applying an appropriate bias to the impurity regions 102. Holes from the substrate 100 are trapped in trap sites inside the charge trapping layer 120. The holes trapped in the charge trapping layer 120 are recombined with extra electrons. In this way, a memory cell is erased.
In such a flash memory device having the SONOS or MANOS structure, after electric charges are injected into the silicon nitride film used as the charge trapping layer 120 in order to program the memory cell, the injected electric charges may be lost through the tunneling layer 110 or the blocking layer 130. An electric charge retention characteristic which represents an ability to retain electric charges trapped in the charge trapping layer 120 for a long time largely depends on characteristics of the silicon nitride film used as the charge trapping layer 120. Therefore, it may be one of the most important factors among data retention characteristics to control the electric charge retention characteristic of the silicon nitride film.
The improvement in data retention characteristics of the charge trap flash memory device may be achieved by improving the electric charge retention characteristic of an ONO stack structure in a fabrication process, for example, by improving the characteristics of the silicon nitride film or improving the leakage current characteristic of the tunneling layer or the blocking layer. In addition to those methods, the improvement in data retention characteristics of the charge trap flash memory device may be achieved by improving a data retention margin through an electrical operation of memory cells. Generally, in programming flash memory cells, the program operation is followed by a program verify operation at a predetermined threshold voltage (Vt) level. After the program operation, a program pass or fail is determined with reference to a read line, which is relatively lower than a program verify voltage.
FIG. 2 illustrates an energy distribution of trap sites included in a silicon nitride film used as a charge trapping layer.
The silicon nitride film used as the charge trapping layer has characteristics of an insulation film, and includes a large number of traps capable of trapping electric charges therein. The traps inside the silicon nitride film are distributed randomly and exhibit a certain range of energy level distribution as illustrated in FIG. 2. Although the silicon nitride film includes a plurality of traps 210 with a relatively high energy level, it also includes traps 220 with a relatively low energy level. The traps 220 with a relatively low energy level trap electric charges through the program and erase operations of the flash memory device, and then the trapped electric charges are easily detrapped or released as a certain time elapses. Consequently, as illustrated in FIG. 3, a threshold voltage of a memory cell is greatly lowered.
FIG. 3 illustrates a variation in a threshold voltage of a memory cell due to loss of electric charges in a charge trap flash memory device.
Since the electric charges trapped in the charge trapping layer by the program operation are detrapped with the elapse of time, the threshold voltage of the memory cell is gradually lowered from a threshold voltage 310 which is given when the memory cell is programmed. Typically, the initial reduction width of the threshold voltage is greatest, and the threshold voltage is gradually lowered with the elapse of time. When the threshold voltage becomes lower than a voltage of a read line, the corresponding memory cell is determined as an unprogrammed memory cell in the read operation. Consequently, a data retention fail may increase.